1 Pages, 124 KB, Original
10 Pages, 1020 KB, Original
28 Pages, 3438 KB, Original
60 Pages, 7988 KB, Original
38 Pages, 645 KB, Original
FPGA, ACT2 Family, Antifuse Switch Tech., OTP, 684 Logic Cells, 568 Reg., 5V Supply, Std Speed Grade, 132PGA
38 Pages, 645 KB, Original
FPGA, ACT2 Family, Antifuse Switch Tech., OTP, 684 Logic Cells, 568 Reg., 5V Supply, Std Speed Grade, 132PGA
38 Pages, 645 KB, Original
FPGA, ACT2 Family, Antifuse Switch Tech., OTP, 684 Logic Cells, 568 Reg., 5V Supply, 1 Speed Grade, 132PGA
38 Pages, 645 KB, Original
FPGA, ACT2 Family, Antifuse Switch Tech., OTP, 684 Logic Cells, 568 Reg., 5V Supply, 1 Speed Grade, 132PGA
2 Pages, 55 KB, Original
Development Tools, Evaluation Kit For 64022LV
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type idle low. Class Q. Lead finish optional. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type idle low. Class Q. Lead finish solder. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type idle low. Class V. Lead finish optional. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type 1760, idle low. Class Q. Lead finish optional. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type 1760, idle low. Class V. Lead finish optional. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type 1760, idle low. Class V. Lead finish gold. Total dose none.
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type idle low. Class Q. Lead finish optional. Total dose 3E5 rads(Si).
18 Pages, 354 KB, Original
Monolithic transceiver, 5V operation: SMD. Device type idle low. Class V. Lead finish optional. Total dose 3E5 rads(Si).