HYB25DC256163CE-4, HYB25DC256163CE-5, HYB25DC256163CE-6 Revision History: 2007-01, Rev. 1.1 Page Subjects (major changes since last revision) All Adapted internet edition All Added new speedsort -4 Previous Revision: 2007-01, Rev. 1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-SR4U-HULB 2 Internet Data Sheet HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM 1 Overview This chapter lists all main features of the product family HYB25DC256163CE and the ordering information. 1.1 * * * * * * * * * * * * * * * * * * Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge
1uF C878 1000pF C877 0.1uF C879 10uF 16V L509 MBW3216-501TF C867 0.1uF +2.5V_VDDM_MST R8163 1K +3.3V_MST SW_L/R: COMP2_L/R or SIDE_L/R MSTAR N-EU MSTAR 2007/12/20 8 11 EAX40043807 MSTAR LP81A #9.DDR MDATA[0-15] MDATA[0-15] MDATA[0-15] +2.5V_VDDM_MST IC900 HYB25DC256163CE-4 AR902 56 1/16W C902 0.1uF MDATA[8] VDD_1 DQ0 MDATA[9] VDDQ_1 MDATA[10] DQ1 MDATA[11] DQ2 C903 0.1uF MDATA[12] VSSQ_1 DQ3 DQ4 MDATA[13] VDDQ_2 MDATA[14] DQ5 MDATA[15] DQ6 VSSQ_2 AR903 56 1/16W C904 0.1uF DQ7 NC_1 VDDQ_3 LDQS DQS1 C905 0.1uF A13/NC_2 VDD_2 NC_3 C900 0.1uF LDM UDQM WE WEZ CAS CASZ RAS RASZ CS NC_4 BA0 SBA0 BA1 SBA1 MADR[10] MADR[0] MADR[1] MADR[11] MADR[10] MADR[11] MADR[9] MADR[10] MADR[8] MADR[9] MADR[7] MADR[8] MADR[6] MADR[7] MADR[5] MADR[6] MADR[4] MADR[5] MADR[3] MADR[4] MADR[2] MADR[3] MADR[1] MADR[2] MADR[0] MADR[1] A10/AP MADR[10] A0 MADR[0] A1 MADR[1] MADR[2] MADR[2] MADR[3] MADR[3] A2 A3 VDD_3 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 57 11 56 12 55 13 54 14 53 15 52 16 51 17 50 18 49 19 48 20 47
5DC256[80/16]3C[E/F] 256-Mbit Double-Data-Rate SGRAM TABLE 2 Ordering Information for Lead free Products Product Type Organisation Clock (MHz) Package Note HYB25DC256803CE-4 x8 250 PG-TSOPII-66 1) PG-TFBGA-60 1) HYB25DC256803CE-5 200 HYB25DC256803CE-6 166 HYB25DC256163CE-4 x16 250 HYB25DC256163CE-5 200 HYB25DC256163CE-6 HYB25DC256803CF-4 166 x8 250 HYB25DC256803CF-5 200 HYB25DC256803CF-6 HYB25DC256163CF-4 166 x16 250 HYB25DC256163CF-5 200 HYB25DC256163CF-6 166 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Note: Please check with your Qimonda representative that leadtime and availability of your preferred device type and version meet your project requirements. Rev. 1.30, 2008-03
8V_AVD 0.1uF DQ2 VSSQ_1 C903 0.1uF SCL_Part SDA_Part C1008 0.1uF DQ1 MDATA[11] MDATA[7] C1009 VDDQ_1 MDATA[10] +3.3V DQ15 14 MDATA[9] AR901 56 1/16W VSS_3 66 13 1 DQ0 YMUX0 VDD_1 0.1uF C902 0.1uF C1006 AR902 56 1/16W MDATA[8] C1000 0.1uF MDATA[0-15] IC900 HYB25DC256163CE-4 AVS_1 +2.5V_VDDM_MST C1001 0.01uF MDATA[0-15] C1012 0.01uF R1007 0 27MHz R1005 1M DEC_656[0-7] X1000 20pF C1014 C1005 22pF MAX 1A MADR[4] TW9910 VSS_1 34 C901 0.1uF MADR[0] MADR[0-11] **MULTI ITEM MADR[0-11] MAIN - QIMONDA : EAN41788501 SUB - HYNIX : EAN31729202 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL
Q1 MDATA[10] C903 0.1uF DQ0 VDDQ_1 VDD_1 MDATA[9] C902 0.1uF 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 13 14 55 56 57 58 59 60 61 62 63 64 65 66 12 11 10 9 8 7 6 5 4 3 2 1 IC900 HYB25DC256163CE-4 MDATA[8] AR902 56 1/16W THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MADR[0-11] MDATA[0-15] #9.DDR EAX40043809 MSTAR LP81A C906 0.1uF VSS_1 A4 A5 A6 A7 A8 A9 A11 A12/NC_5 NC_6 CKE CK CK UDM VSS_2 VREF NC_7 UDQS VSSQ_3 NC_8 DQ8 VDDQ_4 READY C907 1000pF R905 150 R906 1K MADR[4] MADR[5] MADR[6] MADR[7] MADR[8] MADR[9] MADR[11] MADR[4] MADR[5] MADR[6] MADR[7] MADR[8] MADR[9] MADR[11] CKE MCLKZ MCLK LDQM DQS0 2008/01/08 9 11 DDR +2.5V_VDDM_MST MSTAR ** MULTI ITEM MAIN - QIMONDA : EAN4178850
REG 3.3V TAS5709 Digital AMP EARPHONE AMP TPA6110 15V LCD (LVDS) MX25L1605 AM2C-15G 24C64 EEPROM +5V SWITCH DUAL FET PSU SPK 2CH 5V_ST SPI_D PANEL_CTL/POWER_ON/OFF +1.25V_ST +5V_TUNER INV_CTL/ DIMMING SW_RESET / IIC_AMP EAR_LR_OUT/MUTE IIC_PART SPI_CZ/CLK HYB25DC256163CE-4 LVA[0:3] / LVB[0:3] / LVACLK/ LVBCLK MDATA[0:15] MADR[0:11] TMDS/DDC/ HDMI_SEL/HDMI_IIC HDMI S/W TMDS351PAG RGB/HVS/IIC_DSUB DDC SC_VIN/ID1/FB/RGB SCART_LRIN PC_AUD 24C02BN EEPROM HDMI3_5V_DET(HPD) HDMI 1,2 TMDS/DDC/HPD_S/W DDC 24C02BN 24C02BN EEPROM 24C02BN EEPROM EEPROM PANEL_POWER BLOCK DIAGRAM LGE Internal Use Only DESCRIPTION OF BLOCK DIAGRAM 1.Input Interface. 1-1.PC Input - RGB Input is directly transmitted to LGE1854C(scaler,Clock 12Mhz) and display up to 1920*1080 resolution - DVI Signal input go to scaler through TMSD351(DVI/HDMI Switch) - PC Audio is connected PC-Audio input by Stereo Cable 1-2 Video Input - Component :YPbPr/YCbCr signal input, Up to 1080P Resolution. - CVBS/S-Video : CVBS/S-Video signal input, suppo