eue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Functional Diagram) for KSZ8864CNX/RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Automotive version of the KSZ8864RMNUB are also available (see the Ordering Information section).The KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs c

eue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Functional Diagram) for KSZ8864CNX/RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Automotive version of the KSZ8864RMNUB are also available (see the Ordering Information section).The KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs c

four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Figure 1-1) for KSZ8864CNX/ RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Automotive version of the KSZ8864RMNUB are also available (see Section "Product Identification System").The KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of th

four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII (see Figure 1-1) for KSZ8864CNX/ RMNUB data interface. An industrial temperature-grade version of the KSZ8864CNXIA and a qualified AEC-Q100 Automotive version of the KSZ8864RMNUB are also available (see the Product Information System section).The KSZ8864CNX/RMNUB provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864CNX/RMNUB consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864CNX/RMNUB contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the